1. Field of the Invention
This invention relates to an apparatus for testing semiconductor devices particularly with respect to wirebond integrity. The present invention also relates to a method of testing semiconductor devices.
2. Description of the Related Art
All semiconductor devices have at least one junction which exhibits such a voltage-to-current characteristic as shown in FIG. 4 of the accompanying drawings. The voltage drop for a typical semiconductor junction is in the region of 0.5-0.8 volts at about 1.0 mA at room temperature.
However, a semiconductor device cannot provide its intended function or characteristic if any of bondwires is improperly bonded. For instance, an open bondwire would result in an infinite voltage drop across it, and what can be measured is the compliance of the current source. Conversely, a short circuit occurring across two bondwires would result in a zero voltage drop.
Further, a semiconductor device may also suffer a resistive short across two bondwires. As shown in FIG. 5, the resistive short exhibits a linear voltage-to-current characteristic which is easily distinguishable from the characteristic of a good semiconductor junction.
In this way, since the state of the wirebonds greatly affects the property of a semiconductor device, it is critically necessary to test the semiconductor device for its wirebond integrity. A prior art tester for this purpose is disclosed in Japanese Patent Application No. 57-189075 (Laid-open; Nov. 20, 1982) for example.
According to the laid-open Japanese application identified above, a predetermined current is supplied through a selected pin (lead) of a semiconductor device under test (DUT) with the remaining pins held grounded. A resulting voltage drop across the selected pin is then compared with a reference voltage drop which is generated by a reference voltage generator, and the difference between the two voltage drops is used for determining whether the wirebond associated with the selected pin is good or not. Apparently, a similar operation is repeated with respect to every pin of the DUT to determine whether the semiconductor device as a whole is acceptable.
However, the prior art tester discussed above has been found to suffer a major drawback that the reference voltage generator need be re-programmed to generate a suitable reference voltage every time a differently designed semiconductor device is to be tested. Further, it is also necessary to newly set tolerable limits for the different semiconductor device.